Responsibilities

1.Develop verification plans and methodologies.

2.Responsible for the construction and maintenance of module-level and subsystem-level verification environments.

3.Perform chip functional and performance verification.

4.Check verification coverage and perform verification optimization.

5.Write comprehensive verification reports.

6.Assist software engineers in the development and optimization of test software.

7.Participate in post-silicon validation and testing as required.

Qualifications: 

1.Master’s degree or higher in Electronic Engineering or a related field, with over 5 years of relevant chip verification experience.

2.Familiar with Linux environment and UVM methodology; capable of performing module-level or system-level verification and building verification environments.

3.Able to generate verification plans, code, and functional coverage reports according to project requirements, and complete verification documentation.

4.Maintain verification environment; proficient in at least one scripting language (Python/Makefile/Shell); familiar with verification flow; collaborate with design engineers to debug and resolve design issues.

5.Familiar with RTL simulation and gate-level simulation flows, with relevant debugging skills.

6.Hands-on experience with SystemVerilog Assertions (SVA) is preferred.

7.Strong analytical and problem-solving skills, with excellent communication abilities.

8.Team coordination skills, capable of collaborating with cross-functional teams to drive task completion.

9.Experience with CMOS Image Sensor related projects is highly preferred.